`timescale 1ns/1ns
module bus_wr_tb;
reg clk;
reg cs;
reg wr;
reg [31:0] addr;
reg [31:0] data;

initial begin
    cs = 1'b1;
    wr = 1'b1;
    #30; @(posedge clk)
    bus_wr(32'h1100008a,32'h11113000);
    bus_wr(32'h1100009a,32'h11113001);
    bus_wr(32'h110000aa,32'h11113002);
    bus_wr(32'h110000ba,32'h11113003);
    bus_wr(32'h110000ca,32'h11113004);
    addr = 32'bx;
    data= 32'bx;
end

initial clk = 1'b1;
always #5 clk = ~clk;

task bus_wr;
    input[31:0] ADDR;
    input[31:0] DATA;
    begin
    cs = 1'b0; wr = 1'b0; addr = ADDR; data = DATA;
    @(posedge clk);
    @(posedge clk);
    @(posedge clk) cs = 1'b1; wr = 1'b1;
    end
endtask

/*iverilog */
initial begin
    $dumpfile("bus_wr_tb.vcd"); //生成的 vcd 文件名称
    $dumpvars(0, bus_wr_tb); //测试模块名称
    #300 $finish;
end

endmodule